This invention relates to Magnetoresistive Random Access Memories (MRAMs), and more particularly to architectures for MRAMs.
In any memory type, including MRAMs, there is a continuing desire to reduce the memory size and increase performance. One important aspect of performance is the speed with which the memory is read and programmed (written). Speed limitations include such things as the performance of the bit cell and the capacitance of the lines running through the array. A variety of techniques have been developed to improve these characteristics. For example, memory arrays have commonly been divided into subarrays so that no single line is excessively capacitive. This can also reduce power consumption. Such techniques in MRAMs have been developed to reduce the capacitance of bit lines by collecting cells into a group of cells. A global bit line is selectively coupled to only the group that is selected. This coupling has the beneficial effect of reducing the number of memory cells that were coupled to the global bit line.
MRAM memories require currents in metal lines above and below the magnetic tunnel junction to generate magnetic fields that write data to the bit cell. The magnetic fields change the polarization of the magnetic materials in the magnetic tunnel junction changing the state of the bit cell and thus the resistance of the tunnel junction. Placement of the metal lines conducting currents that are used to generate magnetic fields for an MRAM cell relative to the magnetic tunnel junction affects the characteristics of the desired magnetic field. However, a technique for grouping cells to improve the read efficiency involves the addition of a metal line between the tunnel junction and another metal line used for writing the cell. The additional metal line moves the metal line used for writing the cell away from the tunnel junction, thereby reducing the efficiency of the writing. Thus, with this technique, an improvement in read speed is offset by a decrease in write efficiency. The promise of MRAMs is, however, that of a universal memory that can be both high speed and non-volatile.